Infineon TRAVEO T2G - 23.9.14 SCB_I2 C_CTRL

Technical Reference Manual 002-29852 Rev. *B
23.9.14 SCB_I2C_CTRL
Description:
I2C control
Address:
0x40600060
Offset:
0x60
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0xFB88
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name LOW_PHASE_OVS [7:4] HIGH_PHASE_OVS [3:0]
Bits 15 14 13 12 11 10 9 8
Name S_NOT
_READY
_DATA_NA
CK [15:15]
S_NOT
_READY
_ADDR_NA
CK [14:14]
S_READY
_DATA
_ACK
[13:13]
S_READY
_ADDR
_ACK
[12:12]
S
_GENERAL
_IGNORE
[11:11]
None
[10:10]
M_NOT
_READY
_DATA_NA
CK [9:9]
M_READY
_DATA
_ACK [8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:17] LOOPBACK
[16:16]
Bits 31 30 29 28 27 26 25 24
Name MASTER
_MODE
[31:31]
SLAVE
_MODE
[30:30]
None [29:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:3 HIGH_PHASE_OVS RW R 8 Serial I2C interface high phase oversampling factor.
HIGH_PHASE_OVS + 1 SCB clock periods constitute
the high phase of a bit period. The valid range is [5,
15] with input signal median filtering and [4, 15] without
input signal median filtering.
The field is only used in master mode. In slave mode,
the field is NOT used. However, there is a frequency
requirement for the SCB clock wrt. the regular
interface (IF) high time to guarantee functional correct
behavior. With input signal median filtering, the IF high
time should be >= 6 SCB clock cycles and <= 16 SCB
clock cycles. Without input signal median filtering, the
IF high time should be >= 5 SCB clock cycles and <=
16 SCB clock cycles.
1406
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers