Infineon TRAVEO T2G - Page 1407

Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
4:7 LOW_PHASE_OVS RW R 8 Serial I2C interface low phase oversampling factor.
LOW_PHASE_OVS + 1 SCB clock periods constitute
the low phase of a bit period. The valid range is [7, 15]
with input signal median filtering and [6, 15] without
input signal median filtering.
The field is only used in master mode. In slave mode,
the field is NOT used. However, there is a frequency
requirement for the SCB clock wrt. the regular (no
stretching) interface (IF) low time to guarantee
functionally correct behavior. With input signal median
filtering, the IF low time should be >= 8 SCB clock
cycles and <= 16 IP clock cycles. Without input signal
median filtering, the IF low time should be >= 7 SCB
clock cycles and <= 16 SCB clock cycles.
in slave mode, this field is used to define number of
clk_scb cycles for tSU-DAT timing (from
ACK/NACK/data ready, to SCL rising edge (released
from I2C slave clock stretching))
8 M_READY_DATA_ACK RW R 1 When '1', a received data element by the master is
immediately ACK'd when the receiver FIFO is not full.
9 M_NOT_READY_DATA
_NACK
RW R 1 When '1', a received data element byte the master is
immediately NACK'd when the receiver FIFO is full.
When '0', clock stretching is used instead (till the
receiver FIFO is no longer full).
11 S_GENERAL_IGNORE RW R 1 When '1', a received general call slave address is
immediately NACK'd (no ACK or clock stretching) and
treated as a non matching slave address. This is
useful for slaves that do not need any data supplied
within the general call structure.
12 S_READY_ADDR_ACK RW R 1 When '1', a received (matching) slave address is
immediately ACK'd when the receiver FIFO is not full.
In EZ mode, this field should be set to '1'.
13 S_READY_DATA_ACK RW R 1 When '1', a received data element by the slave is
immediately ACK'd when the receiver FIFO is not full.
In EZ mode, this field should be set to '1'.
1407
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers