Infineon TRAVEO T2G - 3.8.3.9 CM0 P_SCS_IPR

Technical Reference Manual 002-29852 Rev. *B
3.8.3.9 CM0P_SCS_IPR
Description:
Interrupt Priority Registers
Address:
0xE000E400
Offset:
0x400
Retention:
Retained
IsDeepSleep:
No
Comment:
Sets or reads interrupt priorities. Register n contains priorities for interrupts N=4n .. 4n+3
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name PRI_N0 [7:6] None [5:0]
Bits 15 14 13 12 11 10 9 8
Name PRI_N1 [15:14] None [13:8]
Bits 23 22 21 20 19 18 17 16
Name PRI_N2 [23:22] None [21:16]
Bits 31 30 29 28 27 26 25 24
Name PRI_N3 [31:30] None [29:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
6:7 PRI_N0 RW R 0 Priority of interrupt number N.
14:15 PRI_N1 RW R 0 Priority of interrupt number N+1.
22:23 PRI_N2 RW R 0 Priority of interrupt number N+2.
30:31 PRI_N3 RW R 0 Priority of interrupt number N+3.
170
2022-04-18
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