Infineon TRAVEO T2G - 3.8.3.15 CM0 P_SCS_CCR

Technical Reference Manual 002-29852 Rev. *B
3.8.3.15 CM0P_SCS_CCR
Description:
Configuration and Control Register
Address:
0xE000ED14
Offset:
0xD14
Retention:
Retained
IsDeepSleep:
No
Comment:
Returns configuration and control data.
Default:
0x208
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:4] UNALIGN
_TRP [3:3]
None [2:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:10] STKALIGN
[9:9]
None [8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
3 UNALIGN_TRP R 1 1: unaligned word and halfword accesses generate a
HardFault exception.
9 STKALIGN R 1 1: On exception entry, the SP used prior to the
exception is adjusted to be 8-byte aligned and the
context to restore it is saved. The SP is restored on the
associated exception return.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers