Infineon TRAVEO T2G - 23.9.8 SCB_SPI_RX_CTRL

Technical Reference Manual 002-29852 Rev. *B
23.9.8 SCB_SPI_RX_CTRL
Description:
SPI receiver control
Address:
0x4060002C
Offset:
0x2C
Retention:
Retained
IsDeepSleep:
No
Comment:
Only applies in SPI MOTOROLA submode, internally clocked SPI operation.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:6] PARITY
_ENABLED
[5:5]
PARITY
[4:4]
None [3:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:9] DROP_ON
_PARITY
_ERROR
[8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
4 PARITY RW R 0 Parity bit. When '0', the receiver expects an even
parity. When '1', the receiver expects an odd parity.
5 PARITY_ENABLED RW R 0 Parity checking enabled ('1') or not ('0').
8 DROP_ON_PARITY
_ERROR
RW R 0 Behavior when a parity check fails. When '0', received
data is send to the RX FIFO. When '1', received data is
dropped and lost.
1397
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers