Infineon TRAVEO T2G - 3.8.6.35 CM0 P_CTI_PID1

Technical Reference Manual 002-29852 Rev. *B
3.8.6.35 CM0P_CTI_PID1
Description:
Peripheral Identification Register 1
Address:
0xF0002FE4
Offset:
0xFE4
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0xB9
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name VALUE [7:0]
Bits 15 14 13 12 11 10 9 8
Name VALUE [15:8]
Bits 23 22 21 20 19 18 17 16
Name VALUE [23:16]
Bits 31 30 29 28 27 26 25 24
Name VALUE [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 VALUE R R 185 N/A
265
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers