Infineon TRAVEO T2G - 2.3.9.3 CANFD_CH_RXFTOP0_DATA

Technical Reference Manual 002-29852 Rev. *B
2.3.9.3 CANFD_CH_RXFTOP0_DATA
Description:
Receive FIFO 0 Top Data
Address:
0x405201A8
Offset:
0x1A8
Retention:
Retained
IsDeepSleep:
No
Comment:
Read side effect, except if read from debug host
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name F0TD [7:0]
Bits 15 14 13 12 11 10 9 8
Name F0TD [15:8]
Bits 23 22 21 20 19 18 17 16
Name F0TD [23:16]
Bits 31 30 29 28 27 26 25 24
Name F0TD [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 F0TD R W Undefined When enabled (F0TPE=1) read data from MRAM at
location FnTA. This register can have a read side
effect if the following conditions are met:
- M_TTCAN not being reconfigured (CCCR.CCE=0)
- FIFO Top Pointer logic is enabled (FnTPE=1)
- FIFO is not empty (FnFL!=0)
The read side effect is as follows:
- if FnMWC pointed to the last word of the message
(as indicated by FnDS) then the corresponding
message index (FnGI) is automatically acknowledge
by a write to FnAI
- FnMWC is incremented (or restarted if FnMWC
pointed to the last word of the message)
- the FIFO top address FnTA is incremented (with
FIFO wrap around)
When this logic is disabled (F0TPE=0) a Read from
this register returns undefined data.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers