Infineon TRAVEO T2G - 14.2.2 FLASHC_FLASH_PWR_CTL

Technical Reference Manual 002-29852 Rev. *B
14.2.2 FLASHC_FLASH_PWR_CTL
Description:
Flash power control
Address:
0x40240004
Offset:
0x4
Retention:
Retained
IsDeepSleep:
No
Comment:
This register controls Flash memory power control input pins 'enable' and 'enable_hv'. Flash
memory can turned OFF through SW in LPACTIVE power mode by making ENABLE=0 and
ENABLE_HV=0. The wakeup time of the Flash memory is 10us (Twake1). So, SW has to wait
for 10us to read from Flash after turning the Flash memory ON though this register.
Default:
0x3
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:2] ENABLE
_HV [1:1]
ENABLE
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 ENABLE RW R 1 Enables power to the flash memory
1 ENABLE_HV RW R 1 Enables HV power to the flash memory
939
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers