Infineon TRAVEO T2G - 9.1.1.35 CH_STRUCT 34; 9.1.1.36 CH_STRUCT 35; 9.1.1.37 CH_STRUCT 36; 9.1.1.38 CH_STRUCT 37

Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
DW0_CH_STRUCT33_TR_CMD
0x40288868 FULL Channel software trigger
9.1.1.35 CH_STRUCT 34
Register Name Address Permission Description
DW0_CH_STRUCT34_CH_CTL
0x40288880 FULL Channel control
DW0_CH_STRUCT34_CH_STATUS
0x40288884 FULL Channel status
DW0_CH_STRUCT34_CH_IDX
0x40288888 FULL Channel current indices
DW0_CH_STRUCT34_CH_CURR_PTR
0x4028888C FULL Channel current descriptor pointer
DW0_CH_STRUCT34_INTR
0x40288890 FULL Interrupt
DW0_CH_STRUCT34_INTR_SET
0x40288894 FULL Interrupt set
DW0_CH_STRUCT34_INTR_MASK
0x40288898 FULL Interrupt mask
DW0_CH_STRUCT34_INTR_MASKED
0x4028889C FULL Interrupt masked
DW0_CH_STRUCT34_SRAM_DATA0
0x402888A0 FULL SRAM data 0
DW0_CH_STRUCT34_SRAM_DATA1
0x402888A4 FULL SRAM data 1
DW0_CH_STRUCT34_TR_CMD
0x402888A8 FULL Channel software trigger
9.1.1.36 CH_STRUCT 35
Register Name Address Permission Description
DW0_CH_STRUCT35_CH_CTL
0x402888C0 FULL Channel control
DW0_CH_STRUCT35_CH_STATUS
0x402888C4 FULL Channel status
DW0_CH_STRUCT35_CH_IDX
0x402888C8 FULL Channel current indices
DW0_CH_STRUCT35_CH_CURR_PTR
0x402888CC FULL Channel current descriptor pointer
DW0_CH_STRUCT35_INTR
0x402888D0 FULL Interrupt
DW0_CH_STRUCT35_INTR_SET
0x402888D4 FULL Interrupt set
DW0_CH_STRUCT35_INTR_MASK
0x402888D8 FULL Interrupt mask
DW0_CH_STRUCT35_INTR_MASKED
0x402888DC FULL Interrupt masked
DW0_CH_STRUCT35_SRAM_DATA0
0x402888E0 FULL SRAM data 0
DW0_CH_STRUCT35_SRAM_DATA1
0x402888E4 FULL SRAM data 1
DW0_CH_STRUCT35_TR_CMD
0x402888E8 FULL Channel software trigger
9.1.1.37 CH_STRUCT 36
Register Name Address Permission Description
DW0_CH_STRUCT36_CH_CTL
0x40288900 FULL Channel control
DW0_CH_STRUCT36_CH_STATUS
0x40288904 FULL Channel status
DW0_CH_STRUCT36_CH_IDX
0x40288908 FULL Channel current indices
DW0_CH_STRUCT36_CH_CURR_PTR
0x4028890C FULL Channel current descriptor pointer
DW0_CH_STRUCT36_INTR
0x40288910 FULL Interrupt
DW0_CH_STRUCT36_INTR_SET
0x40288914 FULL Interrupt set
DW0_CH_STRUCT36_INTR_MASK
0x40288918 FULL Interrupt mask
DW0_CH_STRUCT36_INTR_MASKED
0x4028891C FULL Interrupt masked
DW0_CH_STRUCT36_SRAM_DATA0
0x40288920 FULL SRAM data 0
DW0_CH_STRUCT36_SRAM_DATA1
0x40288924 FULL SRAM data 1
DW0_CH_STRUCT36_TR_CMD
0x40288928 FULL Channel software trigger
9.1.1.38 CH_STRUCT 37
Register Name Address Permission Description
DW0_CH_STRUCT37_CH_CTL
0x40288940 FULL Channel control
DW0_CH_STRUCT37_CH_STATUS
0x40288944 FULL Channel status
DW0_CH_STRUCT37_CH_IDX
0x40288948 FULL Channel current indices
DW0_CH_STRUCT37_CH_CURR_PTR
0x4028894C FULL Channel current descriptor pointer
DW0_CH_STRUCT37_INTR
0x40288950 FULL Interrupt
DW0_CH_STRUCT37_INTR_SET
0x40288954 FULL Interrupt set
DW0_CH_STRUCT37_INTR_MASK
0x40288958 FULL Interrupt mask
DW0_CH_STRUCT37_INTR_MASKED
0x4028895C FULL Interrupt masked
DW0_CH_STRUCT37_SRAM_DATA0
0x40288960 FULL SRAM data 0
DW0_CH_STRUCT37_SRAM_DATA1
0x40288964 FULL SRAM data 1
DW0_CH_STRUCT37_TR_CMD
0x40288968 FULL Channel software trigger
9.1.1.39 CH_STRUCT 38
Register Name Address Permission Description
DW0_CH_STRUCT38_CH_CTL
0x40288980 FULL Channel control
DW0_CH_STRUCT38_CH_STATUS
0x40288984 FULL Channel status
DW0_CH_STRUCT38_CH_IDX
0x40288988 FULL Channel current indices
835
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers