Infineon TRAVEO T2G - 14.2.26 FLASHC_DMAC_BUFF_CTL

Technical Reference Manual 002-29852 Rev. *B
14.2.26 FLASHC_DMAC_BUFF_CTL
Description:
DMA controller buffer control
Address:
0x40240680
Offset:
0x680
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x40000000
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None
[31:31]
PREF_EN
[30:30]
None [29:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
30 PREF_EN RW R 1 See CRYPTO_BUFF_CTL.
963
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers