Infineon TRAVEO T2G - 9.3.18.3 DW_CH_STRUCT_CH_IDX

Technical Reference Manual 002-29852 Rev. *B
9.3.18.3 DW_CH_STRUCT_CH_IDX
Description:
Channel current indices
Address:
0x40288008
Offset:
0x8
Retention:
Retained
IsDeepSleep:
No
Comment:
Note that this register is retained during DeepSleep system power mode.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name X_IDX [7:0]
Bits 15 14 13 12 11 10 9 8
Name Y_IDX [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 X_IDX RW RW Undefined Specifies the X loop index. In the range of [0,
X_COUNT], with X_COUNT taken from the current
descriptor.
Note: HW sets this field to '0' when it updates the
current descriptor pointer CH_CURR_PTR with
DESCR_NEXT_PTR after execution of the current
descriptor.
Note: SW should set this field to '0' when it updates
CH_CURR_PTR.
8:15 Y_IDX RW RW Undefined Specifies the Y loop index, with X_COUNT taken from
the current descriptor.
Note: HW sets this field to '0' when it updates the
current descriptor pointer CH_CURR_PTR with
DESCR_NEXT_PTR after execution of the current
descriptor.
Note: SW should set this field to '0' when it updates
CH_CURR_PTR.
882
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers