Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
PASS0_SAR2_CH2_GRP_STAT
0x409028A8 FULL Group status register
PASS0_SAR2_CH2_ENABLE
0x409028B8 FULL Enable register
PASS0_SAR2_CH2_TR_CMD
0x409028BC FULL Software triggers
19.3.4 CH 3
Register Name Address Permission Description
PASS0_SAR2_CH3_TR_CTL
0x409028C0 FULL Trigger control.
PASS0_SAR2_CH3_SAMPLE_CTL
0x409028C4 FULL Sample control.
PASS0_SAR2_CH3_POST_CTL
0x409028C8 FULL Post processing control
PASS0_SAR2_CH3_RANGE_CTL
0x409028CC FULL Range thresholds
PASS0_SAR2_CH3_INTR
0x409028D0 FULL Interrupt request register.
PASS0_SAR2_CH3_INTR_SET
0x409028D4 FULL Interrupt set request register
PASS0_SAR2_CH3_INTR_MASK
0x409028D8 FULL Interrupt mask register.
PASS0_SAR2_CH3_INTR_MASKED
0x409028DC FULL Interrupt masked request register
PASS0_SAR2_CH3_WORK
0x409028E0 FULL Working data register
PASS0_SAR2_CH3_RESULT
0x409028E4 FULL Result data register
PASS0_SAR2_CH3_GRP_STAT
0x409028E8 FULL Group status register
PASS0_SAR2_CH3_ENABLE
0x409028F8 FULL Enable register
PASS0_SAR2_CH3_TR_CMD
0x409028FC FULL Software triggers
19.3.5 CH 4
Register Name Address Permission Description
PASS0_SAR2_CH4_TR_CTL
0x40902900 FULL Trigger control.
PASS0_SAR2_CH4_SAMPLE_CTL
0x40902904 FULL Sample control.
PASS0_SAR2_CH4_POST_CTL
0x40902908 FULL Post processing control
PASS0_SAR2_CH4_RANGE_CTL
0x4090290C FULL Range thresholds
PASS0_SAR2_CH4_INTR
0x40902910 FULL Interrupt request register.
PASS0_SAR2_CH4_INTR_SET
0x40902914 FULL Interrupt set request register
PASS0_SAR2_CH4_INTR_MASK
0x40902918 FULL Interrupt mask register.
PASS0_SAR2_CH4_INTR_MASKED
0x4090291C FULL Interrupt masked request register
PASS0_SAR2_CH4_WORK
0x40902920 FULL Working data register
PASS0_SAR2_CH4_RESULT
0x40902924 FULL Result data register
PASS0_SAR2_CH4_GRP_STAT
0x40902928 FULL Group status register
PASS0_SAR2_CH4_ENABLE
0x40902938 FULL Enable register
PASS0_SAR2_CH4_TR_CMD
0x4090293C FULL Software triggers
19.3.6 CH 5
Register Name Address Permission Description
PASS0_SAR2_CH5_TR_CTL
0x40902940 FULL Trigger control.
PASS0_SAR2_CH5_SAMPLE_CTL
0x40902944 FULL Sample control.
PASS0_SAR2_CH5_POST_CTL
0x40902948 FULL Post processing control
PASS0_SAR2_CH5_RANGE_CTL
0x4090294C FULL Range thresholds
PASS0_SAR2_CH5_INTR
0x40902950 FULL Interrupt request register.
PASS0_SAR2_CH5_INTR_SET
0x40902954 FULL Interrupt set request register
PASS0_SAR2_CH5_INTR_MASK
0x40902958 FULL Interrupt mask register.
PASS0_SAR2_CH5_INTR_MASKED
0x4090295C FULL Interrupt masked request register
PASS0_SAR2_CH5_WORK
0x40902960 FULL Working data register
PASS0_SAR2_CH5_RESULT
0x40902964 FULL Result data register
PASS0_SAR2_CH5_GRP_STAT
0x40902968 FULL Group status register
PASS0_SAR2_CH5_ENABLE
0x40902978 FULL Enable register
PASS0_SAR2_CH5_TR_CMD
0x4090297C FULL Software triggers
19.3.7 CH 6
Register Name Address Permission Description
PASS0_SAR2_CH6_TR_CTL
0x40902980 FULL Trigger control.
PASS0_SAR2_CH6_SAMPLE_CTL
0x40902984 FULL Sample control.
PASS0_SAR2_CH6_POST_CTL
0x40902988 FULL Post processing control
PASS0_SAR2_CH6_RANGE_CTL
0x4090298C FULL Range thresholds
PASS0_SAR2_CH6_INTR
0x40902990 FULL Interrupt request register.
PASS0_SAR2_CH6_INTR_SET
0x40902994 FULL Interrupt set request register
PASS0_SAR2_CH6_INTR_MASK
0x40902998 FULL Interrupt mask register.
PASS0_SAR2_CH6_INTR_MASKED
0x4090299C FULL Interrupt masked request register
PASS0_SAR2_CH6_WORK
0x409029A0 FULL Working data register
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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