Infineon TRAVEO T2G - 23.9.52 SCB_INTR_RX_MASKED

Technical Reference Manual 002-29852 Rev. *B
23.9.52 SCB_INTR_RX_MASKED
Description:
Receiver interrupt masked request
Address:
0x40600FCC
Offset:
0xFCC
Retention:
Not Retained
IsDeepSleep:
No
Comment:
When read, this register reflects a bitwise and between the interrupt request and mask
registers. This register allows SW to read the status of all mask enabled interrupt causes with
a single load operation, rather than two load operations: one for the interrupt causes and one
for the masks. This simplifies Firmware development. The associated interrupt is active ('1'),
when INTR_RX_MASKED != 0.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name BLOCKED
[7:7]
UNDERFLOW
[6:6]
OVERFLOW
[5:5]
None [4:4] FULL [3:3] NOT
_EMPTY
[2:2]
None [1:1] TRIGGER
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:12] BREAK
_DETECT
[11:11]
BAUD
_DETECT
[10:10]
PARITY
_ERROR
[9:9]
FRAME
_ERROR
[8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 TRIGGER R W 0 Logical and of corresponding request and mask bits.
2 NOT_EMPTY R W 0 Logical and of corresponding request and mask bits.
3 FULL R W 0 Logical and of corresponding request and mask bits.
5 OVERFLOW R W 0 Logical and of corresponding request and mask bits.
6 UNDERFLOW R W 0 Logical and of corresponding request and mask bits.
7 BLOCKED R W 0 Logical and of corresponding request and mask bits.
8 FRAME_ERROR R W 0 Logical and of corresponding request and mask bits.
9 PARITY_ERROR R W 0 Logical and of corresponding request and mask bits.
10 BAUD_DETECT R W 0 Logical and of corresponding request and mask bits.
11 BREAK_DETECT R W 0 Logical and of corresponding request and mask bits.
1454
2022-04-18
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