Infineon TRAVEO T2G - 2.3.9.6.57 CANFD_CH_TTILS

Technical Reference Manual 002-29852 Rev. *B
2.3.9.6.57 CANFD_CH_TTILS
Description:
TT Interrupt Line Select
Address:
0x40520128
Offset:
0x128
Retention:
Retained
IsDeepSleep:
No
Comment:
The TT Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag
from the TT Interrupt Register to one of the two module interrupt lines. For interrupt generation
the respective interrupt line has to be enabled via ILE.EINT0 and ILE.EINT1. 0= TT interrupt
assigned to interrupt line m_ttcan_int0 1= TT interrupt assigned to interrupt line m_ttcan_int1
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name GTWL [7:7] SWEL [6:6] TTMIL [5:5] RTMIL [4:4] SOGL [3:3] CSML [2:2] SMCL [1:1] SBCL [0:0]
Bits 15 14 13 12 11 10 9 8
Name IWTL
[15:15]
ELCL
[14:14]
SE2L
[13:13]
SE1L
[12:12]
TXOL
[11:11]
TXUL
[10:10]
GTEL [9:9] GTDL [8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:19] CERL
[18:18]
AWL_
[17:17]
WTL [16:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0 SBCL RW R 0 Start of Basic Cycle Interrupt Select
0= Assign to interrupt enabled by ILE.EINT0
1= Assign to interrupt enabled by ILE.EINT1
1 SMCL RW R 0 Start of Matrix Cycle Interrupt Select
0= Assign to interrupt enabled by ILE.EINT0
1= Assign to interrupt enabled by ILE.EINT1
2 CSML RW R 0 Change of Synchronization Mode Interrupt Select
0= Assign to interrupt enabled by ILE.EINT0
1= Assign to interrupt enabled by ILE.EINT1
3 SOGL RW R 0 Start of Gap Interrupt Select
0= Assign to interrupt enabled by ILE.EINT0
1= Assign to interrupt enabled by ILE.EINT1
4 RTMIL RW R 0 Register Time Mark Interrupt Select
0= Assign to interrupt enabled by ILE.EINT0
1= Assign to interrupt enabled by ILE.EINT1
5 TTMIL RW R 0 Trigger Time Mark Event Internal Select
0= Assign to interrupt enabled by ILE.EINT0
1= Assign to interrupt enabled by ILE.EINT1
6 SWEL RW R 0 Stop Watch Event Interrupt Select
0= Assign to interrupt enabled by ILE.EINT0
1= Assign to interrupt enabled by ILE.EINT1
7 GTWL RW R 0 Global Time Wrap Interrupt Select
0= Assign to interrupt enabled by ILE.EINT0
1= Assign to interrupt enabled by ILE.EINT1
8 GTDL RW R 0 Global Time Discontinuity Interrupt Select
0= Assign to interrupt enabled by ILE.EINT0
1= Assign to interrupt enabled by ILE.EINT1
9 GTEL RW R 0 Global Time Error Interrupt Select
0= Assign to interrupt enabled by ILE.EINT0
1= Assign to interrupt enabled by ILE.EINT1
118
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers