Infineon TRAVEO T2G - 8.5.3.12 DMAC_CH_DESCR_X_INCR

Technical Reference Manual 002-29852 Rev. *B
8.5.3.12 DMAC_CH_DESCR_X_INCR
Description:
Channel descriptor X increment
Address:
0x402A1070
Offset:
0x70
Retention:
Not Retained
IsDeepSleep:
No
Comment:
Copy of DESCR_X_INCR of the currently active descriptor.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name SRC_X [7:0]
Bits 15 14 13 12 11 10 9 8
Name SRC_X [15:8]
Bits 23 22 21 20 19 18 17 16
Name DST_X [23:16]
Bits 31 30 29 28 27 26 25 24
Name DST_X [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:15 SRC_X R W Undefined Specifies increment of source address for each X loop
iteration (in multiples of SRC_TRANSFER_SIZE). This
field is a signed number (sign-magnitude format) in the
range [-32768, 32767]. If this field is '0', the source
address is not incremented. This is useful for reading
from RX FIFO structures.
16:31 DST_X R W Undefined Specifies increment of destination address for each X
loop iteration (in multiples of DST_TRANSFER_SIZE).
This field is a signed number (sign-magnitude format)
in the range [-32768, 32767]. If this field is '0', the
destination address is not incremented. This is useful
for writing to TX FIFO structures.
819
2022-04-18
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