Technical Reference Manual 002-29852 Rev. *B
23.9.15 SCB_I2C_STATUS
Description:
I2C status
Address:
0x40600064
Offset:
0x64
Retention:
Not Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:6] M_READ
[5:5]
S_READ
[4:4]
None [3:3] I2CS_IC_B
USY [2:2]
I2C_EC_BU
SY [1:1]
BUS_BUSY
[0:0]
Bits 15 14 13 12 11 10 9 8
Name CURR_EZ_ADDR [15:8]
Bits 23 22 21 20 19 18 17 16
Name BASE_EZ_ADDR [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 BUS_BUSY R W 0 I2C bus is busy. The bus is considered busy ('1'), from
the time a START is detected or from the time the SCL
line is '0'. The bus is considered idle ('0'), from the time
a STOP is detected. If SCB block is disabled,
BUS_BUSY is '0'. After enabling the block, it takes
time for the BUS_BUSY to detect a busy bus. This
time is the maximum high time of the SCL line. For a
100 kHz interface frequency, this maximum high time
may last roughly 5 us (half a bit period).
For single master systems, BUS_BUSY does not have
to be used to detect an idle bus before a master starts
a transfer using I2C_M_CMD.M_START (no bus
collisions).
For multi-master systems, BUS_BUSY can be used to
detect an idle bus before a master starts a transfer
using I2C_M_CMD.M_START_ON_IDLE (to prevent
bus collisions).
1 I2C_EC_BUSY R W Undefined Indicates whether the externally clocked logic is
potentially accessing the EZ memory and/or updating
BASE_EZ_ADDR or CURR_EZ_ADDR (this is only
possible in EZ mode). This bit can be used by SW to
determine whether BASE_EZ_ADDR and
CURR_EZ_ADDR are reliable.
2 I2CS_IC_BUSY R W 0 Indicates whether the internally clocked slave logic is
being accessed by external I2C master.
--set at ADDR_MATCH
--clear at START/RESET, STOP detection, or
BUS_ERROR
This bit can be used by SW to determine whether
I2CS_IC is busy before entering DeepSleep.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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