Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
4 S_READ R W 0 I2C slave read transfer ('1') or I2C slave write transfer
('0'). When the I2C slave is inactive/idle or receiving
START, REPEATED START, STOP or an address,
this field is '0''.
5 M_READ R W 0 I2C master read transfer ('1') or I2C master write
transfer ('0'). When the I2C master is inactive/idle or
transmitting START, REPEATED START, STOP or an
address, this field is '0''.
8:15 CURR_EZ_ADDR R W Undefined I2C slave current EZ address. Current address pointer.
This field is only reliable in internally clocked mode. In
externally clocked mode the field may be unreliable
(during an ongoing transfer when I2C_EC_BUSY is
'1'), as clock domain synchronization is not performed
in the design.
16:23 BASE_EZ_ADDR R W Undefined I2C slave base EZ address. Address as provided by
an I2C write transfer. This field is only reliable in
internally clocked mode. In externally clocked mode
the field may be unreliable, as clock domain
synchronization is not performed in the design.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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