Infineon TRAVEO T2G - 14.2 Register Details; 14.2.1 FLASHC_FLASH_CTL

Technical Reference Manual 002-29852 Rev. *B
14.2 Register Details
14.2.1 FLASHC_FLASH_CTL
Description:
Control
Address:
0x40240000
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x110000
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:4] MAIN_WS [3:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:14] WORK
_BANK
_MODE
[13:13]
MAIN
_BANK
_MODE
[12:12]
None [11:10] WORK
_MAP [9:9]
MAIN_MAP
[8:8]
Bits 23 22 21 20 19 18 17 16
Name None
[23:23]
WORK
_ERR_
SILENT
[22:22]
WORK
_ECC_INJ
_EN [21:21]
WORK
_ECC_EN
[20:20]
None
[19:19]
MAIN_ERR
_SILENT
[18:18]
MAIN_ECC
_INJ_EN
[17:17]
MAIN_ECC
_EN [16:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:3 MAIN_WS RW R 0 FLASH macro main interface wait states:
'0': 0 wait states.
...
'15': 15 wait states
8 MAIN_MAP RW R 0 Specifies mapping of FLASH macro main array.
0: Mapping A.
1: Mapping B.
This field is only used when MAIN_BANK_MODE is '1'
(dual bank mode).
9 WORK_MAP RW R 0 Specifies mapping of FLASH macro work array.
0: Mapping A.
1: Mapping B.
This field is only used when WORK_BANK_MODE is
'1' (dual bank mode).
12 MAIN_BANK_MODE RW R 0 Specifies bank mode of FLASH macro main array.
0: Single bank mode.
1: Dual bank mode.
13 WORK_BANK_MODE RW R 0 Specifies bank mode of FLASH macro work array.
0: Single bank mode.
1: Dual bank mode.
16 MAIN_ECC_EN RW R 1 Enable ECC checking for FLASH main interface:
0: Disabled. ECC checking/reporting on FLASH main
interface is disabled. No correctable or non-correctable
faults are reported.
1: Enabled.
936
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers