Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
TCPWM0_GRP0_CNT29_INTR_SET
0x40380EF4 FULL Interrupt set request register
TCPWM0_GRP0_CNT29_INTR_MASK
0x40380EF8 FULL Interrupt mask register
TCPWM0_GRP0_CNT29_INTR_MASKED
0x40380EFC FULL Interrupt masked request register
28.1.31 CNT 30
Register Name Address Permission Description
TCPWM0_GRP0_CNT30_CTRL
0x40380F00 FULL Counter control register
Note:AUTO_RELOAD_LINE_SEL CC0_MATCH_UP_EN
CC0_MATCH_DOWN_EN CC1_MATCH_UP_EN
CC1_MATCH_DOWN_EN are not available for this
register
TCPWM0_GRP0_CNT30_STATUS
0x40380F04 FULL Counter status register
Note:DT_CNT_H is not available for this register
TCPWM0_GRP0_CNT30_COUNTER
0x40380F08 FULL Counter count register
TCPWM0_GRP0_CNT30_CC0
0x40380F10 FULL Counter compare/capture 0 register
TCPWM0_GRP0_CNT30_CC0_BUFF
0x40380F14 FULL Counter buffered compare/capture 0 register
TCPWM0_GRP0_CNT30_CC1
0x40380F18 FULL Counter compare/capture 1 register
TCPWM0_GRP0_CNT30_CC1_BUFF
0x40380F1C FULL Counter buffered compare/capture 1 register
TCPWM0_GRP0_CNT30_PERIOD
0x40380F20 FULL Counter period register
TCPWM0_GRP0_CNT30_PERIOD_BUFF
0x40380F24 FULL Counter buffered period register
TCPWM0_GRP0_CNT30_DT
0x40380F30 FULL Counter PWM dead time register
Note:DT_LINE_OUT_H DT_LINE_COMPL_OUT are not
available for this register
TCPWM0_GRP0_CNT30_TR_CMD
0x40380F40 FULL Counter trigger command register
TCPWM0_GRP0_CNT30_TR_IN_SEL0
0x40380F44 FULL Counter input trigger selection register 0
TCPWM0_GRP0_CNT30_TR_IN_SEL1
0x40380F48 FULL Counter input trigger selection register 1
TCPWM0_GRP0_CNT30_TR_IN_EDGE_SEL
0x40380F4C FULL Counter input trigger edge selection register
TCPWM0_GRP0_CNT30_TR_PWM_CTRL
0x40380F50 FULL Counter trigger PWM control register
TCPWM0_GRP0_CNT30_TR_OUT_SEL
0x40380F54 FULL Counter output trigger selection register
TCPWM0_GRP0_CNT30_INTR
0x40380F70 FULL Interrupt request register
TCPWM0_GRP0_CNT30_INTR_SET
0x40380F74 FULL Interrupt set request register
TCPWM0_GRP0_CNT30_INTR_MASK
0x40380F78 FULL Interrupt mask register
TCPWM0_GRP0_CNT30_INTR_MASKED
0x40380F7C FULL Interrupt masked request register
28.1.32 CNT 31
Register Name Address Permission Description
TCPWM0_GRP0_CNT31_CTRL
0x40380F80 FULL Counter control register
Note:AUTO_RELOAD_LINE_SEL CC0_MATCH_UP_EN
CC0_MATCH_DOWN_EN CC1_MATCH_UP_EN
CC1_MATCH_DOWN_EN are not available for this
register
TCPWM0_GRP0_CNT31_STATUS
0x40380F84 FULL Counter status register
Note:DT_CNT_H is not available for this register
TCPWM0_GRP0_CNT31_COUNTER
0x40380F88 FULL Counter count register
TCPWM0_GRP0_CNT31_CC0
0x40380F90 FULL Counter compare/capture 0 register
TCPWM0_GRP0_CNT31_CC0_BUFF
0x40380F94 FULL Counter buffered compare/capture 0 register
TCPWM0_GRP0_CNT31_CC1
0x40380F98 FULL Counter compare/capture 1 register
TCPWM0_GRP0_CNT31_CC1_BUFF
0x40380F9C FULL Counter buffered compare/capture 1 register
TCPWM0_GRP0_CNT31_PERIOD
0x40380FA0 FULL Counter period register
TCPWM0_GRP0_CNT31_PERIOD_BUFF
0x40380FA4 FULL Counter buffered period register
TCPWM0_GRP0_CNT31_DT
0x40380FB0 FULL Counter PWM dead time register
Note:DT_LINE_OUT_H DT_LINE_COMPL_OUT are not
available for this register
TCPWM0_GRP0_CNT31_TR_CMD
0x40380FC0 FULL Counter trigger command register
TCPWM0_GRP0_CNT31_TR_IN_SEL0
0x40380FC4 FULL Counter input trigger selection register 0
TCPWM0_GRP0_CNT31_TR_IN_SEL1
0x40380FC8 FULL Counter input trigger selection register 1
TCPWM0_GRP0_CNT31_TR_IN_EDGE_SEL
0x40380FCC FULL Counter input trigger edge selection register
TCPWM0_GRP0_CNT31_TR_PWM_CTRL
0x40380FD0 FULL Counter trigger PWM control register
TCPWM0_GRP0_CNT31_TR_OUT_SEL
0x40380FD4 FULL Counter output trigger selection register
TCPWM0_GRP0_CNT31_INTR
0x40380FF0 FULL Interrupt request register
TCPWM0_GRP0_CNT31_INTR_SET
0x40380FF4 FULL Interrupt set request register
TCPWM0_GRP0_CNT31_INTR_MASK
0x40380FF8 FULL Interrupt mask register
TCPWM0_GRP0_CNT31_INTR_MASKED
0x40380FFC FULL Interrupt masked request register
28.1.33 CNT 32
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers