Infineon TRAVEO T2G - 26.8.51 WDT; 26.8.51.1 WDT_CTL

Technical Reference Manual 002-29852 Rev. *B
26.8.51 WDT
26.8.51.1 WDT_CTL
Description:
WDT Control Register
Address:
0x4026C000
Offset:
0x0
Retention:
Retained
IsDeepSleep:
Yes
Comment:
Control register for watchdog. Writes are ignored when locked (i.e. Corresponding
LOCK.WDT_LOCK<>0).
Default:
0x80000001
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:1] ENABLED
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name ENABLE
[31:31]
None [30:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0 ENABLED R RW 1 Indicates actual state of watchdog. May lag ENABLE
by up to three clk_ilo0 cycles.
31 ENABLE RW A 1 Enable watchdog. May take up to three clk_ilo0 cycles
to take effect. When ENABLE changes from 1->0, the
counter is cleared. Do not enter DEEPSLEEP or
HIBERNATE mode if ENABLE<>ENABLED. This can
be done by waiting until ENABLE==ENABLED
whenever ENABLE is changed.
0: Counter is disabled (not clocked).
1: Counter is enabled (counting up)
1723
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers