Infineon TRAVEO T2G - 20.30 Register Details; 20.30.1 PERI_TIMEOUT_CTL

Technical Reference Manual 002-29852 Rev. *B
20.30 Register Details
20.30.1 PERI_TIMEOUT_CTL
Description:
Timeout control
Address:
0x40000200
Offset:
0x200
Retention:
Retained
IsDeepSleep:
No
Comment:
The presence of the TIMEOUT_CTL register is dependent on the TIMEOUT_PRESENT
parameter.
The presence of TIMEOUT_CTL requires slave 0 of the peripheral group to be present
(SL0_PRESENT must be '1').
Default:
0xFFFF
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name TIMEOUT [7:0]
Bits 15 14 13 12 11 10 9 8
Name TIMEOUT [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:15 TIMEOUT RW R 65535 This field specifies a number of clock cycles
(clk_slow). If an AHB-Lite bus transfer takes more than
the specified number of cycles (timeout detection), the
bus transfer is terminated with an AHB-Lite bus error
and a fault is generated (and possibly recorded in the
fault report structure(s)).
'0x0000'-'0xfffe': Number of clock cycles.
'0xffff': This value is the default/reset value and
specifies that no timeout detection is performed: a bus
transfer will never be terminated and a fault will never
be generated.
1140
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers