Infineon TRAVEO T2G - 13.5.1.13 FAULT_STRUCT_INTR_MASKED

Technical Reference Manual 002-29852 Rev. *B
13.5.1.13 FAULT_STRUCT_INTR_MASKED
Description:
Interrupt masked
Address:
0x402100CC
Offset:
0xCC
Retention:
Not Retained
IsDeepSleep:
No
Comment:
When read, this register reflects 'a bitwise AND' between the INTR and INTR_MASK registers.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:1] FAULT [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 FAULT R W 0 Logical and of corresponding INTR and INTR_MASK
fields.
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