Infineon TRAVEO T2G - 21.504.2.8 PERI_MS_PPU_FX_MS_SIZE

Technical Reference Manual 002-29852 Rev. *B
21.504.2.8 PERI_MS_PPU_FX_MS_SIZE
Description:
Master region, size
Address:
0x40010824
Offset:
0x24
Retention:
Retained
IsDeepSleep:
No
Comment:
MS_SIZE is fixed (non-programmable).
The access privileges for MS_SIZE are determined by MS_ATT0, ..., MS_ATT3.
Default:
0x85000000
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name VALID
[31:31]
None [30:29] REGION_SIZE [28:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
24:28 REGION_SIZE R R 5 This field specifies the size of the master region:
'5': 64 B region
The master region includes the SL_ADDR, SL_SIZE,
SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE,
MS_ATT0, ..., MS_ATT3 registers. Therefore, the
access privileges for all these registers is determined
by MS_ATT0, ..., MS_ATT3.
31 VALID R R 1 Master region enable:
'1': Enabled.
1304
2022-04-18
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