Infineon TRAVEO T2G - 5.1.45 CPUSS_CAL_SUP_CLR

Technical Reference Manual 002-29852 Rev. *B
5.1.45 CPUSS_CAL_SUP_CLR
Description:
Calibration support clear and reset
Address:
0x40201804
Offset:
0x1804
Retention:
Retained
IsDeepSleep:
No
Comment:
Read side effect: reset on read (even when read from debug host)
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name DATA [7:0]
Bits 15 14 13 12 11 10 9 8
Name DATA [15:8]
Bits 23 22 21 20 19 18 17 16
Name DATA [23:16]
Bits 31 30 29 28 27 26 25 24
Name DATA [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 DATA RW1C A 0 Read side effect: when read all bits are cleared, write 1
to clear a specific bit
Note: no exception for the debug host, it also causes
the read side effect
748
2022-04-18
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