Infineon TRAVEO T2G - 5.1.3 CPUSS_CM4_CLOCK_CTL

Technical Reference Manual 002-29852 Rev. *B
5.1.3 CPUSS_CM4_CLOCK_CTL
Description:
CM4 clock control
Address:
0x40200008
Offset:
0x8
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:0]
Bits 15 14 13 12 11 10 9 8
Name FAST_INT_DIV [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
8:15 FAST_INT_DIV RW R 0 Specifies the fast clock divider (from the high
frequency clock 'clk_hf' to the peripheral clock
'clk_fast'). Integer division by (1+FAST_INT_DIV).
Allows for integer divisions in the range [1, 256]
(FAST_INT_DIV is in the range [0, 255]).
Note that this field is retained. However, the counter
that is used to implement the division is not and will be
initialized by HW to '0' when transitioning from
DeepSleep to Active power mode.
704
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers