Infineon TRAVEO T2G - 19.5.1.18.3 PASS_SAR_CH_POST_CTL

Technical Reference Manual 002-29852 Rev. *B
19.5.1.18.3 PASS_SAR_CH_POST_CTL
Description:
Post processing control
Address:
0x40900808
Offset:
0x8
Retention:
Retained
IsDeepSleep:
No
Comment:
Make sure the channel or the IP is disabled before changing this register
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name SIGN_EXT
[7:7]
LEFT_ALIG
N [6:6]
None [5:3] POST_PROC [2:0]
Bits 15 14 13 12 11 10 9 8
Name AVG_CNT [15:8]
Bits 23 22 21 20 19 18 17 16
Name RANGE_MODE [23:22] None
[21:21]
SHIFT_R [20:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:26] TR_DONE
_GRP_VIO
[25:25]
None
[24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:2 POST_PROC RW R Undefined Post processing
NONE 0 No postprocessing
AVG 1 Averaging
AVG_RANGE 2 Averaging followed by Range detect
RANGE 3 Range detect
RANGE_PULSE 4 Range detect followed by pulse detect
RESERVED0 5 N/A
RESERVED1 6 N/A
RESERVED2 7 N/A
6 LEFT_ALIGN RW R Undefined Left or right align data in result[15:0].
0: the data is right aligned in result[11:0], with sign
extension to 16 bits if enabled
1: the data is left aligned in result[15:4] with the lower
nibble 0. Caveat if the result was more than 12 bits
(e.g. after averaging) then the bits above 12 will be
discarded.
7 SIGN_EXT RW R Undefined Output data is sign extended
UNSIGNED 0 Default: result data is unsigned (zero extended if
needed)
SIGNED 1 Result data is signed (sign extended if needed)
1112
2022-04-18
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