Infineon TRAVEO T2G - 2.3.5 CANFD_TS_CTL

Technical Reference Manual 002-29852 Rev. *B
2.3.5 CANFD_TS_CTL
Description:
Time Stamp control register
Address:
0x40521020
Offset:
0x1020
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name PRESCALE [7:0]
Bits 15 14 13 12 11 10 9 8
Name PRESCALE [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name ENABLED
[31:31]
None [30:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:15 PRESCALE RW R 0 Time Stamp counter prescale value.
When enabled divide the Host clock (HCLK) by
PRESCALE+1 to create Time Stamp clock ticks.
31 ENABLED RW R 0 Counter enable bit
0 = Count disabled. Stop counting up and keep the
counter value
1 = Count enabled. Start counting up from the current
value
40
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers