Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
DW0_CH_STRUCT24_TR_CMD
0x40288628 FULL Channel software trigger
9.1.1.26 CH_STRUCT 25
Register Name Address Permission Description
DW0_CH_STRUCT25_CH_CTL
0x40288640 FULL Channel control
DW0_CH_STRUCT25_CH_STATUS
0x40288644 FULL Channel status
DW0_CH_STRUCT25_CH_IDX
0x40288648 FULL Channel current indices
DW0_CH_STRUCT25_CH_CURR_PTR
0x4028864C FULL Channel current descriptor pointer
DW0_CH_STRUCT25_INTR
0x40288650 FULL Interrupt
DW0_CH_STRUCT25_INTR_SET
0x40288654 FULL Interrupt set
DW0_CH_STRUCT25_INTR_MASK
0x40288658 FULL Interrupt mask
DW0_CH_STRUCT25_INTR_MASKED
0x4028865C FULL Interrupt masked
DW0_CH_STRUCT25_SRAM_DATA0
0x40288660 FULL SRAM data 0
DW0_CH_STRUCT25_SRAM_DATA1
0x40288664 FULL SRAM data 1
DW0_CH_STRUCT25_TR_CMD
0x40288668 FULL Channel software trigger
9.1.1.27 CH_STRUCT 26
Register Name Address Permission Description
DW0_CH_STRUCT26_CH_CTL
0x40288680 FULL Channel control
DW0_CH_STRUCT26_CH_STATUS
0x40288684 FULL Channel status
DW0_CH_STRUCT26_CH_IDX
0x40288688 FULL Channel current indices
DW0_CH_STRUCT26_CH_CURR_PTR
0x4028868C FULL Channel current descriptor pointer
DW0_CH_STRUCT26_INTR
0x40288690 FULL Interrupt
DW0_CH_STRUCT26_INTR_SET
0x40288694 FULL Interrupt set
DW0_CH_STRUCT26_INTR_MASK
0x40288698 FULL Interrupt mask
DW0_CH_STRUCT26_INTR_MASKED
0x4028869C FULL Interrupt masked
DW0_CH_STRUCT26_SRAM_DATA0
0x402886A0 FULL SRAM data 0
DW0_CH_STRUCT26_SRAM_DATA1
0x402886A4 FULL SRAM data 1
DW0_CH_STRUCT26_TR_CMD
0x402886A8 FULL Channel software trigger
9.1.1.28 CH_STRUCT 27
Register Name Address Permission Description
DW0_CH_STRUCT27_CH_CTL
0x402886C0 FULL Channel control
DW0_CH_STRUCT27_CH_STATUS
0x402886C4 FULL Channel status
DW0_CH_STRUCT27_CH_IDX
0x402886C8 FULL Channel current indices
DW0_CH_STRUCT27_CH_CURR_PTR
0x402886CC FULL Channel current descriptor pointer
DW0_CH_STRUCT27_INTR
0x402886D0 FULL Interrupt
DW0_CH_STRUCT27_INTR_SET
0x402886D4 FULL Interrupt set
DW0_CH_STRUCT27_INTR_MASK
0x402886D8 FULL Interrupt mask
DW0_CH_STRUCT27_INTR_MASKED
0x402886DC FULL Interrupt masked
DW0_CH_STRUCT27_SRAM_DATA0
0x402886E0 FULL SRAM data 0
DW0_CH_STRUCT27_SRAM_DATA1
0x402886E4 FULL SRAM data 1
DW0_CH_STRUCT27_TR_CMD
0x402886E8 FULL Channel software trigger
9.1.1.29 CH_STRUCT 28
Register Name Address Permission Description
DW0_CH_STRUCT28_CH_CTL
0x40288700 FULL Channel control
DW0_CH_STRUCT28_CH_STATUS
0x40288704 FULL Channel status
DW0_CH_STRUCT28_CH_IDX
0x40288708 FULL Channel current indices
DW0_CH_STRUCT28_CH_CURR_PTR
0x4028870C FULL Channel current descriptor pointer
DW0_CH_STRUCT28_INTR
0x40288710 FULL Interrupt
DW0_CH_STRUCT28_INTR_SET
0x40288714 FULL Interrupt set
DW0_CH_STRUCT28_INTR_MASK
0x40288718 FULL Interrupt mask
DW0_CH_STRUCT28_INTR_MASKED
0x4028871C FULL Interrupt masked
DW0_CH_STRUCT28_SRAM_DATA0
0x40288720 FULL SRAM data 0
DW0_CH_STRUCT28_SRAM_DATA1
0x40288724 FULL SRAM data 1
DW0_CH_STRUCT28_TR_CMD
0x40288728 FULL Channel software trigger
9.1.1.30 CH_STRUCT 29
Register Name Address Permission Description
DW0_CH_STRUCT29_CH_CTL
0x40288740 FULL Channel control
DW0_CH_STRUCT29_CH_STATUS
0x40288744 FULL Channel status
DW0_CH_STRUCT29_CH_IDX
0x40288748 FULL Channel current indices
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers