Infineon TRAVEO T2G - 23.9.22 SCB_TX_FIFO_WR

Technical Reference Manual 002-29852 Rev. *B
23.9.22 SCB_TX_FIFO_WR
Description:
Transmitter FIFO write
Address:
0x40600240
Offset:
0x240
Retention:
Not Retained
IsDeepSleep:
No
Comment:
When the IP is disabled (CTRL.ENABLED is '0') or when the TX FIFO is full, a write to this
register is dropped. This register should only be used in FIFO mode (and not in EZ or
CMD_RESP modes). This register is 'write only'; a read from this register returns '0'.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name DATA [7:0]
Bits 15 14 13 12 11 10 9 8
Name DATA [15:8]
Bits 23 22 21 20 19 18 17 16
Name DATA [23:16]
Bits 31 30 29 28 27 26 25 24
Name DATA [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 DATA W R 0 Data frame written into the transmitter FIFO. Behavior
is similar to that of a PUSH operation. Note that when
CTRL.MEM_WIDTH is '0', only DATA[7:0] are used
and when CTRL.MEM_WIDTH is '1', only DATA[15:0]
are used.
A write to a full TX FIFO sets INTR_TX.OVERFLOW to
'1'.
1420
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers