Infineon TRAVEO T2G - 23.9.24 SCB_RX_FIFO_CTRL

Technical Reference Manual 002-29852 Rev. *B
23.9.24 SCB_RX_FIFO_CTRL
Description:
Receiver FIFO control
Address:
0x40600304
Offset:
0x304
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name TRIGGER_LEVEL [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:18] FREEZE
[17:17]
CLEAR
[16:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 TRIGGER_LEVEL RW R 0 Trigger level. When the receiver FIFO has more
entries than the number of this field, a receiver trigger
event INTR_RX.TRIGGER is generated.
16 CLEAR RW R 0 When '1', the receiver FIFO and receiver shift register
are cleared/invalidated. Invalidation will last for as long
as this field is '1'. If a quick clear/invalidation is
required, the field should be set to '1' and be followed
by a set to '0'. If a clear/invalidation is required for an
extended time period, the field should be set to '1'
during the complete time period.
17 FREEZE RW R 0 When '1', hardware writes to the receiver FIFO have
no effect. Freeze will not advance the RX FIFO write
pointer.
1422
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers