Infineon TRAVEO T2G - 28.4.1.1.17 TCPWM_GRP_CNT_TR_PWM_CTRL

Technical Reference Manual 002-29852 Rev. *B
28.4.1.1.17 TCPWM_GRP_CNT_TR_PWM_CTRL
Description:
Counter trigger PWM control register
Address:
0x40380050
Offset:
0x50
Retention:
Retained
IsDeepSleep:
No
Comment:
Used to control counter 'line_out', 'dt_line_out' and 'dt_line_compl_out' output signals.
Default:
0xFF
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name CC1_MATCH_MODE
[7:6]
UNDERFLOW_MODE
[5:4]
OVERFLOW_MODE [3:2] CC0_MATCH_MODE
[1:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:1 CC0_MATCH_MODE RW R 3 Determines the effect of a compare match 0 event
(COUNTER equals CC0 register) on the 'line_out'
output signals. Note that INVERT is especially useful
for center aligned pulse width modulation.
To generate a duty cycle of 0 percent, the counter CC0
register should be set to '0'. For a 100 percent duty
cycle, the counter CC0 register should be set to larger
than the counter PERIOD register.
SET 0 Set to '1'
CLEAR 1 Set to '0'
INVERT 2 Invert
NO_CHANGE 3 No Change
2:3 OVERFLOW_MODE RW R 3 Determines the effect of a counter overflow event
(COUNTER reaches PERIOD) on the 'line_out' output
signals.
SET 0 Set to '1'
CLEAR 1 Set to '0'
INVERT 2 Invert
NO_CHANGE 3 No Change
4:5 UNDERFLOW_MODE RW R 3 Determines the effect of a counter underflow event
(COUNTER reaches '0') on the 'line_out' output
signals.
SET 0 Set to '1'
CLEAR 1 Set to '0'
INVERT 2 Invert
NO_CHANGE 3 No Change
6:7 CC1_MATCH_MODE RW R 3 Determines the effect of a compare match 1 event
(COUNTER equals CC1 register) on the 'line_out'
output signals.
SET 0 Set to '1'
CLEAR 1 Set to '0'
INVERT 2 Invert
1816
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers