Technical Reference Manual 002-29852 Rev. *B
26.8.50.3 MCWDT_CTR2_CONFIG
Description:
MCWDT Subcounter 2 Configuration register
Address:
0x40268084
Offset:
0x84
Retention:
Retained
IsDeepSleep:
Yes
Comment:
Configuration for MCWDT subcounter 2. Writes are ignored when locked (i.e. corresponding
LOCK.MCWDT_LOCK<>0). This register may be written while the counter is running, but new
values may take up to 2 clk_lf cycles to take effect. Before changing the limit, it is
recommended to set the service bit for this subcounter and wait until it reads back low. This
prevents possible unintended actions caused by synchronization delays.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:1] ACTION
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:21] BITS [20:16]
Bits 31 30 29 28 27 26 25 24
Name DEBUG
_RUN
[31:31]
SLEEPDEEP
_PAUSE
[30:30]
None
[29:29]
DEBUG
_TRIGGER
_EN [28:28]
None [27:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 ACTION RW R 0 Action taken when the specified BIT toggles.
Action will be triggered on the same edge where BITS
to observe toggle.
NOTHING 0 Do nothing
INT 1 Trigger an interrupt
16:20 BITS RW R 0 Bit to observe for a toggle:
0: Do ACTION after CNT[0] toggles (i.e. every tick)
.
31: Do ACTION after CNT[31] toggles (i.e. every 2^31
ticks)
28 DEBUG_TRIGGER_EN RW R 0 Enables the trigger input for this MCWDT to pause the
counter during debug mode. To pause at a breakpoint
while debugging, configure the trigger matrix to
connect the related CPU halted signal to the trigger
input for this MCWDT, and then set this bit. It takes up
to two clk_lf cycles for the trigger signal to be
processed. Triggers that are less than two clk_lf cycles
may be missed. Synchronization errors can
accumulate each time it is halted.
0: Pauses the counter whenever a debug probe is
connected.
1: Pauses the counter whenever a debug probe is
connected and the trigger input is high.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers