Infineon TRAVEO T2G - 2.3.9.6.6 CANFD_CH_CCCR

Technical Reference Manual 002-29852 Rev. *B
2.3.9.6.6 CANFD_CH_CCCR
Description:
CC Control Register
Address:
0x40520018
Offset:
0x18
Retention:
Retained
IsDeepSleep:
No
Comment:
Protected Write
Default:
0x1
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name TEST [7:7] DAR [6:6] MON_ [5:5] CSR [4:4] CSA [3:3] ASM [2:2] CCE [1:1] INIT [0:0]
Bits 15 14 13 12 11 10 9 8
Name NISO
[15:15]
TXP [14:14] EFBI
[13:13]
PXHD
[12:12]
None [11:10] BRSE [9:9] FDOE [8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 INIT RW R 1 Initialization
0= Normal Operation
1= Initialization is started
1 CCE RW R 0 Configuration Change Enable
0= The CPU has no write access to the protected
configuration registers
1= The CPU has write access to the protected
configuration registers (while CCCR.INIT = '1')
2 ASM RW R 0 Restricted Operation Mode
Bit ASM can only be set by the Host when both CCE
and INIT are set to '1'. The bit can be reset by
the Host at any time. For a description of the
Restricted Operation Mode see Section 3.1.5.
0= Normal CAN operation
1= Restricted Operation Mode active
3 CSA RW R 0 Clock Stop Acknowledge
0= No clock stop acknowledged
1= M_TTCAN may be set in power down by stopping
m_ttcan_hclk and m_ttcan_cclk
4 CSR RW R 0 Clock Stop Request, not supported by M_TTCAN use
CTL.STOP_REQ at the group level instead.
0= No clock stop is requested
1= Clock stop requested. When clock stop is
requested, first INIT and then CSA will be set after
all pending transfer requests have been completed
and the CAN bus reached idle.
5 MON_ RW R 0 Bus Monitoring Mode
Bit MON can only be set by the Host when both CCE
and INIT are set to '1'. The bit can be reset by
the Host at any time.
0= Bus Monitoring Mode is disabled
1= Bus Monitoring Mode is enabled
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers