Technical Reference Manual 002-29852 Rev. *B
26.8.5 CLK_OUTPUT_SLOW
Description:
Slow Clock Output Select Register
Address:
0x40260144
Offset:
0x144
Retention:
Retained
IsDeepSleep:
Yes
Comment:
Selects a slow clock for calibration. The outputs of these muxes go into CLK_OUTPUT_FAST.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name SLOW_SEL1 [7:4] SLOW_SEL0 [3:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:3 SLOW_SEL0 RW R 0 Select signal for slow clock output #0
NC 0 Disabled - output is 0. For power savings, clocks are
blocked before entering any muxes.
ILO0 1 Internal Low Speed Oscillator (ILO0)
WCO 2 Watch-Crystal Oscillator (WCO)
BAK 3 Root of the Backup domain clock tree (BAK)
ALTLF 4 Alternate low-frequency clock input to SRSS (ALTLF)
LFCLK 5 Root of the low-speed clock tree (LFCLK)
IMO 6 Internal Main Oscillator (IMO). This is grouped with the
slow clocks so it can be observed during DEEPSLEEP
entry/exit.
SLPCTRL 7 Sleep Controller clock (SLPCTRL). This is grouped
with the slow clocks so it can be observed during
DEEPSLEEP entry/exit.
PILO 8 Precision Internal Low Speed Oscillator (PILO)
ILO1 9 Internal Low Speed Oscillator (ILO1), if present on the
product.
ECO_PRESCALER 10 ECO Prescaler (ECO_PRESCALER)
LPECO 11 LPECO
LPECO_PRESCALER 12 LPECO Prescaler (LPECO_PRESCALER)
4:7 SLOW_SEL1 RW R 0 Select signal for slow clock output #1
NC 0 Disabled - output is 0. For power savings, clocks are
blocked before entering any muxes.
ILO0 1 Internal Low Speed Oscillator (ILO)
WCO 2 Watch-Crystal Oscillator (WCO)
BAK 3 Root of the Backup domain clock tree (BAK)
ALTLF 4 Alternate low-frequency clock input to SRSS (ALTLF)
LFCLK 5 Root of the low-speed clock tree (LFCLK)
IMO 6 Internal Main Oscillator (IMO). This is grouped with the
slow clocks so it can be observed during DEEPSLEEP
entry/exit.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers