Infineon TRAVEO T2G - Page 1633

Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
SLOW_SEL1 7 Selects the output of
CLK_OUTPUT_SLOW.SLOW_SEL1
20:23 PATH_SEL1 RW R 0 Selects a clock path to use in fast clock output #1
logic.
0: FLL output
1-15: PLL output on path1-path15 (if available)
24:27 HFCLK_SEL1 RW R 0 Selects a HFCLK tree for use in fast clock output #1
logic
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers