Infineon TRAVEO T2G - 7.5.3.15 CXPI_CH_RX_FIFO_RD

Technical Reference Manual 002-29852 Rev. *B
7.5.3.15 CXPI_CH_RX_FIFO_RD
Description:
RX FIFO read
Address:
0x405180A8
Offset:
0xA8
Retention:
Not Retained
IsDeepSleep:
No
Comment:
This register supports a single 32-bit access to read data fields.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name DATA [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 DATA R W Undefined Received Data field. Software uses this data field.
HW shadows the first content of the RX FIFO to this
field. Software reading this field will remove the
content from the RX FIFO and the next content of the
RX FIFO will be shadowed over to this field. This field
is 8bits and reflects the width of the RX FIFO. Software
needs to rely on the RXPID_FI.FI/RXPID_FI.DLCEXT
fields to determine number of bytes. Note that, during
debug, a read from test controller would not
remove/destory the content.
Software needs to ensure it does not read from this
field if there is no available content (from
RX_FIFO_STATUS.USED). Otherwise, the content is
undefined and it would result in RX FIFO underflow
error. (INTR.RX_UNDERFLOW_ERROR).
788
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers