Technical Reference Manual 002-29852 Rev. *B
7.5.3.12 CXPI_CH_TX_FIFO_WR
Description:
TX FIFO write
Address:
0x40518088
Offset:
0x88
Retention:
Not Retained
IsDeepSleep:
No
Comment:
This register supports 32-bit access only
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name DATA [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 DATA W R 0 Transmit Data field.
Transmission: To be transmitted data field. SW
provides data field.
HW shadows over the write data to TX FIFO after SW
performs a write to this field.
HW shadows the whole 8 bits to the TX FIFO and
relies on the TXPID_FI.FI/TXPID_FI.DCLEXT to
determine the number of bytes.
SW needs to ensure that TX FIFO is not overwritten
before the content is consumed by HW by checking
TX_FIFO_STATUS.AVAIL. Otherwise, the previous
content would be overwritten and resulting in TX
FIFO's overflow error
(INTR.TX_OVERFLOW_ERROR).
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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