Infineon TRAVEO T2G - 14.2.13 FLASHC_CM0_CA_STATUS1

Technical Reference Manual 002-29852 Rev. *B
14.2.13 FLASHC_CM0_CA_STATUS1
Description:
CM0+ cache status 1
Address:
0x40240444
Offset:
0x444
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name TAG [7:0]
Bits 15 14 13 12 11 10 9 8
Name TAG [15:8]
Bits 23 22 21 20 19 18 17 16
Name TAG [23:16]
Bits 31 30 29 28 27 26 25 24
Name TAG [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 TAG R W Undefined Cache line address of the cache line specified by
CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR.
950
2022-04-18
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