Infineon TRAVEO T2G - 23.9.50 SCB_INTR_RX_SET

Technical Reference Manual 002-29852 Rev. *B
23.9.50 SCB_INTR_RX_SET
Description:
Receiver interrupt set request
Address:
0x40600FC4
Offset:
0xFC4
Retention:
Not Retained
IsDeepSleep:
No
Comment:
When read, this register reflects the interrupt request register.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name BLOCKED
[7:7]
UNDERFLOW
[6:6]
OVERFLOW
[5:5]
None [4:4] FULL [3:3] NOT
_EMPTY
[2:2]
None [1:1] TRIGGER
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:12] BREAK
_DETECT
[11:11]
BAUD
_DETECT
[10:10]
PARITY
_ERROR
[9:9]
FRAME
_ERROR
[8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 TRIGGER RW1S A 0 Write with '1' to set corresponding bit in interrupt
request register.
2 NOT_EMPTY RW1S A 0 Write with '1' to set corresponding bit in interrupt status
register.
3 FULL RW1S A 0 Write with '1' to set corresponding bit in interrupt status
register.
5 OVERFLOW RW1S A 0 Write with '1' to set corresponding bit in interrupt status
register.
6 UNDERFLOW RW1S A 0 Write with '1' to set corresponding bit in interrupt status
register.
7 BLOCKED RW1S A 0 Write with '1' to set corresponding bit in interrupt status
register.
8 FRAME_ERROR RW1S A 0 Write with '1' to set corresponding bit in interrupt status
register.
9 PARITY_ERROR RW1S A 0 Write with '1' to set corresponding bit in interrupt status
register.
10 BAUD_DETECT RW1S A 0 Write with '1' to set corresponding bit in interrupt status
register.
11 BREAK_DETECT RW1S A 0 Write with '1' to set corresponding bit in interrupt status
register.
1452
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers