Infineon TRAVEO T2G - 3.8.3.24 CM0 P_SCS_MPU_RASR

Technical Reference Manual 002-29852 Rev. *B
3.8.3.24 CM0P_SCS_MPU_RASR
Description:
MPU Region Attribute and Size Register
Address:
0xE000EDA0
Offset:
0xDA0
Retention:
Retained
IsDeepSleep:
No
Comment:
Defines the size, access behavior, and memory type of the region identified by MPU_RNR,
and enables that region.
Used with MPU_RBAR, see MPU Region Number Register, MPU_RNR on. Writing a SIZE
value greater than the maximum size supported by the corresponding MPU_RBAR has an
UNPREDICTABLE effect. The smallest supported region size is 256 bytes. This restricts the
lowest possible value of SIZE.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:6] SIZE [5:1] ENABLE
[0:0]
Bits 15 14 13 12 11 10 9 8
Name SRD [15:8]
Bits 23 22 21 20 19 18 17 16
Name ATTRS [23:16]
Bits 31 30 29 28 27 26 25 24
Name ATTRS [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 ENABLE RW R X Enables this region:
0: when the MPU is enabled, this region is disabled.
1: When the MPU is enabled, this region is enabled.
Enabling a region has no effect unless the
MPU_CTRL.ENABLE bit is set to 1, to enable the
MPU.
1:5 SIZE RW R X Indicates the region size.
The permitted values for SIZE are 7-31, that is
0b00111-0b11111. The associated region size, in
bytes, is 2^(SIZE+1). SIZE field values less than 7 are
reserved, because the smallest supported region size
is 256 bytes.
8:15 SRD RW R X Subregion Disable. For regions of 256 bytes or larger,
each bit of this field controls whether one of the eight
equal subregions is enabled.
0: subregion enabled.
1: subregion disabled.
16:31 ATTRS RW R X The MPU Region Attribute field, This field has the
following subfields, defined in Region attribute control
on Arm TRM page B3-300 of the ARMv6M
Architecture manual (September 2010 version):
XN MPU_RASR[28]
AP[2:0] MPU_RASR[26:24]
TEX[2:0] MPU_RASR[21:19]
S MPU_RASR[18]
C MPU_RASR[17]
B MPU_RASR[16]
185
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers