Infineon TRAVEO T2G - 3.8.6.7 CM0 P_CTI_CTIOUTEN

Technical Reference Manual 002-29852 Rev. *B
3.8.6.7 CM0P_CTI_CTIOUTEN
Description:
CTI Channel to Trigger Enable Registers
Address:
0xF00020A0
Offset:
0xA0
Retention:
Retained
IsDeepSleep:
No
Comment:
The CTI Channel to Trigger Enable Registers define which channels can generate a
CTITRIGOUT output. There is one register for each of the eight CTITRIGOUT outputs. Within
each register there is one bit for each of the four channels implemented. These registers affect
the mapping from application trigger to trigger outputs.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:4] TRIGOUTEN [3:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:3 TRIGOUTEN RW R 0 Changing the value of this bit from a 0 to a 1 enables a
channel event for the corresponding channel to
generate an CTITRIGOUT output:
0 = the channel input (CTICHIN) from the CTM is not
routed to the CTITRIGOUT output 1 = the channel
input (CTICHIN) from the CTM is routed to the
CTITRIGOUT output. There is one bit for each of the
four channels. For example in register CTIOUTEN0,
enabling bit 0 enables CTICHIN[0] to cause a trigger
event on the CTITRIGOUT[0] output.
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2022-04-18
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