Infineon TRAVEO T2G - 15.25.7.13 GPIO_PRT_CFG_OUT

Technical Reference Manual 002-29852 Rev. *B
15.25.7.13 GPIO_PRT_CFG_OUT
Description:
Port output buffer configuration register
Address:
0x4031004C
Offset:
0x4C
Retention:
Retained
IsDeepSleep:
No
Comment:
Configures the output driver for each pin.
Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the
peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before setting the IO drive
mode to avoid producing glitches on the bus.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name SLOW7
[7:7]
SLOW6
[6:6]
SLOW5
[5:5]
SLOW4
[4:4]
SLOW3
[3:3]
SLOW2
[2:2]
SLOW1
[1:1]
SLOW0
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name DRIVE_SEL3 [23:22] DRIVE_SEL2 [21:20] DRIVE_SEL1 [19:18] DRIVE_SEL0 [17:16]
Bits 31 30 29 28 27 26 25 24
Name DRIVE_SEL7 [31:30] DRIVE_SEL6 [29:28] DRIVE_SEL5 [27:26] DRIVE_SEL4 [25:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 SLOW0 RW R 0 Enables slow slew rate for IO pin 0
'0': Fast slew rate
'1': Slow slew rate
1 SLOW1 RW R 0 Enables slow slew rate for IO pin 1
2 SLOW2 RW R 0 Enables slow slew rate for IO pin 2
3 SLOW3 RW R 0 Enables slow slew rate for IO pin 3
4 SLOW4 RW R 0 Enables slow slew rate for IO pin 4
5 SLOW5 RW R 0 Enables slow slew rate for IO pin 5
6 SLOW6 RW R 0 Enables slow slew rate for IO pin 6
7 SLOW7 RW R 0 Enables slow slew rate for IO pin 7
16:17 DRIVE_SEL0 RW R 0 Documentation:
Note: DRIVE_SELx are used among GPIO cells and
HSIO_STD but the encoding values may differ as
shown on the right side of this table
DRIVE_SEL_ZERO 0 Traveo II: GPIO_STD/GPIO_ENH: Full drive strengh:
GPIO drives current at its max rated spec.
Traveo II:_GPIO_SMC: GPIO_SMC default mode.
Traveo II:_HSIO_STD: HSIO default mode.
PSoC 6: GPIO cells and HSIO_STD cells: Full drive
strength: GPIO drives current at its max rated spec.
DRIVE_SEL_ONE 1 Traveo II: GPIO_STD/GPIO_ENH: Full drive strengh:
GPIO drives current at its max rated spec.
Traveo II:_GPIO_SMC: GPIO full drive strength.
Traveo II:_HSIO_STD: GPIO full drive strength.
PSoC 6: GPIO cells and HSIO_STD cells: 1/2 drive
strength: GPIO drives current at 1/2 of its max rated
spec
1011
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers