Technical Reference Manual 002-29852 Rev. *B
14.2.27.9 FLASHC_FM_DATA
Description:
Flash macro data_in[31 to 0] both Code and Work Flash
Address:
0x4024F040
Offset:
0x40
Retention:
Not Retained
IsDeepSleep:
No
Comment:
These registers support aligned 32-bit accesses. The usage of this register should follow the
PGM sequence defined (and implemented by API). It has restrictions on the FM_ADDR and #
of writes that can be done per pgm command (64,256,page for Code or 32 to work flash) and
therefore the sequence must be correct. These register are related to C interface functionality.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name FM_DATA [7:0]
Bits 15 14 13 12 11 10 9 8
Name FM_DATA [15:8]
Bits 23 22 21 20 19 18 17 16
Name FM_DATA [23:16]
Bits 31 30 29 28 27 26 25 24
Name FM_DATA [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 FM_DATA W RW 0 Pgm command data in going to the internal write buffer
(WBUF).
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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