Infineon TRAVEO T2G - 5.1.40 CPUSS_DP_STATUS

Technical Reference Manual 002-29852 Rev. *B
5.1.40 CPUSS_DP_STATUS
Description:
Debug port status
Address:
0x40201410
Offset:
0x1410
Retention:
Not Retained
IsDeepSleep:
No
Comment:
Default:
0x4
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:3] SWJ_JTAG
_SEL [2:2]
SWJ
_DEBUG
_EN [1:1]
SWJ
_CONNE
CTED [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 SWJ_CONNECTED R W 0 Specifies if the SWJ debug port is connected; i.e.
debug host interface is active:
'0': Not connected/not active.
'1': Connected/active.
1 SWJ_DEBUG_EN R W 0 Specifies if SWJ debug is enabled, i.e.
CDBGPWRUPACK is '1' and thus debug clocks are
on:
'0': Disabled.
'1': Enabled.
2 SWJ_JTAG_SEL R W 1 Specifies if the JTAG or SWD interface is selected.
This signal is valid when DP_CTL.PTM_SEL is '0'
(SWJ mode selected) and SWJ_CONNECTED is '1'
(SWJ is connected).
'0': SWD selected.
'1': JTAG selected.
742
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers