Infineon TRAVEO T2G - 25.6.1.2 SMARTIO_PRT_SYNC_CTL

Technical Reference Manual 002-29852 Rev. *B
25.6.1.2 SMARTIO_PRT_SYNC_CTL
Description:
Synchronization control register
Address:
0x40320010
Offset:
0x10
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name IO_SYNC_EN [7:0]
Bits 15 14 13 12 11 10 9 8
Name CHIP_SYNC_EN [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 IO_SYNC_EN RW R Undefined Synchronization of the IO pin input signals to
'clk_fabric', one bit for each IO pin: IO_SYNC_EN[i] is
for IO pin i.
'0': No synchronization.
'1': Synchronization.
8:15 CHIP_SYNC_EN RW R Undefined Synchronization of the chip input signals to 'clk_fabric',
one bit for each input: CHIP_SYNC_EN[i] is for input i.
'0': No synchronization.
'1': Synchronization.
1618
2022-04-18
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