Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
25 PIPELINE_EN RW R 1 Enable for pipeline register:
'0': Disabled (register is bypassed).
'1': Enabled.
31 ENABLED RW R 0 Enable for programmable IO. Should only be set to '1'
when the programmable IO is completely configured:
'0': Disabled (signals are bypassed; behavior as if
BYPASS is 0xFF). When disabled, the fabric (data unit
and LUTs) reset is activated.
If the IP is disabled:
- The PIPELINE_EN register field should be set to '1',
to ensure low power consumption by preventing
combinatorial loops.
- The CLOCK_SRC register field should be set to '20'-
'30' (clock is constant '0'), to ensure low power
consumption.
'1': Enabled. Once enabled, it takes 3 'clk_fabric' clock
cycles till the fabric reset is de-activated and the fabric
becomes fully functional. This ensures that the IO pins'
input synchronizer states are flushed when the fabric is
fully functional.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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