Infineon TRAVEO T2G - 19.2.10 CH 9; 19.2.11 CH 10; 19.2.12 CH 11; 19.2.13 CH 12

Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
PASS0_SAR1_CH8_INTR_MASKED
0x40901A1C FULL Interrupt masked request register
PASS0_SAR1_CH8_WORK
0x40901A20 FULL Working data register
PASS0_SAR1_CH8_RESULT
0x40901A24 FULL Result data register
PASS0_SAR1_CH8_GRP_STAT
0x40901A28 FULL Group status register
PASS0_SAR1_CH8_ENABLE
0x40901A38 FULL Enable register
PASS0_SAR1_CH8_TR_CMD
0x40901A3C FULL Software triggers
19.2.10 CH 9
Register Name Address Permission Description
PASS0_SAR1_CH9_TR_CTL
0x40901A40 FULL Trigger control.
PASS0_SAR1_CH9_SAMPLE_CTL
0x40901A44 FULL Sample control.
PASS0_SAR1_CH9_POST_CTL
0x40901A48 FULL Post processing control
PASS0_SAR1_CH9_RANGE_CTL
0x40901A4C FULL Range thresholds
PASS0_SAR1_CH9_INTR
0x40901A50 FULL Interrupt request register.
PASS0_SAR1_CH9_INTR_SET
0x40901A54 FULL Interrupt set request register
PASS0_SAR1_CH9_INTR_MASK
0x40901A58 FULL Interrupt mask register.
PASS0_SAR1_CH9_INTR_MASKED
0x40901A5C FULL Interrupt masked request register
PASS0_SAR1_CH9_WORK
0x40901A60 FULL Working data register
PASS0_SAR1_CH9_RESULT
0x40901A64 FULL Result data register
PASS0_SAR1_CH9_GRP_STAT
0x40901A68 FULL Group status register
PASS0_SAR1_CH9_ENABLE
0x40901A78 FULL Enable register
PASS0_SAR1_CH9_TR_CMD
0x40901A7C FULL Software triggers
19.2.11 CH 10
Register Name Address Permission Description
PASS0_SAR1_CH10_TR_CTL
0x40901A80 FULL Trigger control.
PASS0_SAR1_CH10_SAMPLE_CTL
0x40901A84 FULL Sample control.
PASS0_SAR1_CH10_POST_CTL
0x40901A88 FULL Post processing control
PASS0_SAR1_CH10_RANGE_CTL
0x40901A8C FULL Range thresholds
PASS0_SAR1_CH10_INTR
0x40901A90 FULL Interrupt request register.
PASS0_SAR1_CH10_INTR_SET
0x40901A94 FULL Interrupt set request register
PASS0_SAR1_CH10_INTR_MASK
0x40901A98 FULL Interrupt mask register.
PASS0_SAR1_CH10_INTR_MASKED
0x40901A9C FULL Interrupt masked request register
PASS0_SAR1_CH10_WORK
0x40901AA0 FULL Working data register
PASS0_SAR1_CH10_RESULT
0x40901AA4 FULL Result data register
PASS0_SAR1_CH10_GRP_STAT
0x40901AA8 FULL Group status register
PASS0_SAR1_CH10_ENABLE
0x40901AB8 FULL Enable register
PASS0_SAR1_CH10_TR_CMD
0x40901ABC FULL Software triggers
19.2.12 CH 11
Register Name Address Permission Description
PASS0_SAR1_CH11_TR_CTL
0x40901AC0 FULL Trigger control.
PASS0_SAR1_CH11_SAMPLE_CTL
0x40901AC4 FULL Sample control.
PASS0_SAR1_CH11_POST_CTL
0x40901AC8 FULL Post processing control
PASS0_SAR1_CH11_RANGE_CTL
0x40901ACC FULL Range thresholds
PASS0_SAR1_CH11_INTR
0x40901AD0 FULL Interrupt request register.
PASS0_SAR1_CH11_INTR_SET
0x40901AD4 FULL Interrupt set request register
PASS0_SAR1_CH11_INTR_MASK
0x40901AD8 FULL Interrupt mask register.
PASS0_SAR1_CH11_INTR_MASKED
0x40901ADC FULL Interrupt masked request register
PASS0_SAR1_CH11_WORK
0x40901AE0 FULL Working data register
PASS0_SAR1_CH11_RESULT
0x40901AE4 FULL Result data register
PASS0_SAR1_CH11_GRP_STAT
0x40901AE8 FULL Group status register
PASS0_SAR1_CH11_ENABLE
0x40901AF8 FULL Enable register
PASS0_SAR1_CH11_TR_CMD
0x40901AFC FULL Software triggers
19.2.13 CH 12
Register Name Address Permission Description
PASS0_SAR1_CH12_TR_CTL
0x40901B00 FULL Trigger control.
PASS0_SAR1_CH12_SAMPLE_CTL
0x40901B04 FULL Sample control.
PASS0_SAR1_CH12_POST_CTL
0x40901B08 FULL Post processing control
PASS0_SAR1_CH12_RANGE_CTL
0x40901B0C FULL Range thresholds
PASS0_SAR1_CH12_INTR
0x40901B10 FULL Interrupt request register.
PASS0_SAR1_CH12_INTR_SET
0x40901B14 FULL Interrupt set request register
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers