Infineon TRAVEO T2G - 13.5.1.4 FAULT_STRUCT_PENDING0

Technical Reference Manual 002-29852 Rev. *B
13.5.1.4 FAULT_STRUCT_PENDING0
Description:
Fault pending 0
Address:
0x40210040
Offset:
0x40
Retention:
Not Retained
IsDeepSleep:
No
Comment:
The PENDING0, PENDING1, PENDING2 registers specify pending (not captured) fault
sources. The fault source for which data is captured in DATA0 through DATA3 and which is
validated by STATUS.VALID and identified by STATUS.IDX is NOT included in this list of
pending fault sources. When a fault source is captured, its corresponding bit field in
PENDING0/1/2 is set to '0'.
Note that the pending fault sources are the same for ALL fault structures; i.e. these registers
are NOT qualified by the fault structure specific MASK0, MASK1 and MASK2 registers.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name SOURCE [7:0]
Bits 15 14 13 12 11 10 9 8
Name SOURCE [15:8]
Bits 23 22 21 20 19 18 17 16
Name SOURCE [23:16]
Bits 31 30 29 28 27 26 25 24
Name SOURCE [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 SOURCE R W Undefined This field specifies the following sources:
Bit 0: CM0 MPU.
Bit 1: CRYPTO MPU.
Bit 2: DW 0 MPU.
Bit 3: DW 1 MPU.
Bit 4: DMA controller MPU.
...
Bit 15: DAP MPU.
Bit 16: CM4 system bus MPU.
Bit 17: CM4 code bus MPU (for non FLASH controller
accesses).
Bit 18: CM4 code bus MPU (for FLASH controller
accesses).
925
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers