Infineon TRAVEO T2G - 4.13.3.2 CM4_FPB_REMAP

Technical Reference Manual 002-29852 Rev. *B
4.13.3.2 CM4_FPB_REMAP
Description:
FlashPatch Remap register
Address:
0xE0002004
Offset:
0x4
Retention:
Retained
IsDeepSleep:
No
Comment:
The FP_REMAP register characteristics are:
Purpose: Indicates whether the implementation supports flash patch remap, and if it does,
holds the SRAM address for remap.
Usage constraints: There are no usage constraints.
Configurations: Always implemented.
Attributes: See Table C1-23 on Arm TRM page C1-816.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [4:0]
Bits 15 14 13 12 11 10 9 8
Name REMAP [15:8]
Bits 23 22 21 20 19 18 17 16
Name REMAP [23:16]
Bits 31 30 29 28 27 26 25 24
Name RMPSPT [31:30] None
[29:29]
REMAP [28:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
5:28 REMAP RW R 0 If the FPB supports flash patch remap, this field:
- Holds bits[28:5] of the base address in SRAM to
which the FPB remaps the address.
- Has an UNKNOWN value on reset.
If the FPB only supports breakpoint functionality this
field is UNK/SBZP.
30:31 RMPSPT RW R 0 Indicates whether the FPB unit supports flash patch
remap:
0 Remapping not supported. The FPB only supports
breakpoint functionality.
1 Hard-wired remap to SRAM region.
These bits are read only.
370
2022-04-18
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