Technical Reference Manual 002-29852 Rev. *B
2.3 Register Details
2.3.1 CANFD_CTL
Description:
Global CAN control register
Address:
0x40521000
Offset:
0x1000
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name STOP_REQ [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name MRAM
_OFF
[31:31]
None [30:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 STOP_REQ RW R 0 Clock Stop Request for each TTCAN IP .
The m_ttcan_clkstop_req of each TTCAN IP is directly
driven by these bits.
31 MRAM_OFF RW R 0 MRAM off
0= Default MRAM on (with MRAM retained in
DeepSleep).
1= Switch MRAM off (not retained) to save power.
Before setting this bit all the CAN channels have to be
powered down using the STOP_REQ/ACK bits.
When the MRAM is off any access attempt to it is
considered an address error (as if MRAM_SIZE=0).
After switching the MRAM on again software needs to
allow for a certain power up time before MRAM can be
used, i.e. before STOP_REQ can be de-asserted. The
power up time is equivalent to the system SRAM
power up time specified in the
CPUSS.RAM_PWR_DELAY_CTL register.
MRAM_OFF should be set to 0 prior to transitioning to
Hibernate mode.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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